Master Slave D Flip Flop Verilog Code

MASTER-SLAVE D FLIP FLOP

In SR flip-flop when the conditions SET and RESET both are 1 that condition is known as a forbidden condition. This tries to change the both Q and Q’ to be 1 and whichever will turn 1 first will further control the latch which is certainly we don’t want. This can be avoided when both S and R inputs are short-circuited with a not gate in between. This prevents the forbidden condition of S and R to be 1. This combination is what we call D – Flip Flop. Thus we require only single data known as D for this FF. The output Q changes whenever D is applied with any input bit.

Whenever the clock goes from low to high i.e. posedge the input is read and fed to the output. Whenever the clock goes from high to low i.e. negedge the previous output is retained back or in easy words, it remains the same.

The basic D Flip Flop is improved using a Master-Slave condition. Here two D flip-flops are used and the clock of Master D FF is inverted and then fed to the clock of the Slave D FF. The output Q of Master FF is fed to the input D of Slave FF. Thus when the clock goes low to high the Master reads the input and stores the output. During this phase, the Slave FF remains locked.

When the clock goes from High to low the Slave FF gets activated and the Master gets locked. Since during negede Master retains the output thus it acts as input for Slave and output is obtained. Master-Slave condition is used because it avoids the race around the condition of toggling output multiple times in a single clock cycle.

Code for Master-Slave D type FF

module Mas(d,reset,clk,q,qbar);

 input d,clk,reset;

 output q,qbar;

 Master Masterr(d,reset,clk,qx,qbarx);

 Master Slave(qx,reset,!clk,q,qbar);

endmodule

module Master(d,reset,clk,q,qbar);

 input d,reset,clk;

 output reg q,qbar;

 initial

  q = 0;

 always @(posedge clk)begin

  if(~reset)begin

   q <= d;

   qbar <= !d;

  end

  else begin

   q <= 1'bx;

   qbar <= 1'bx;

 end

 end

endmodule

Testbench for Master Slave D FF

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: Shashi Suman
//
// Create Date:   19:30:41 05/12/2025
// Design Name:   Mas
// Module Name:   F:/Season 1/Master/TestMas.v
// Project Name:  Master
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Mas
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module TestMas;

// Inputs
reg d;
reg reset;
reg clk;

// Outputs
wire q;
wire qbar;

// Instantiate the Unit Under Test (UUT)
Mas uut (
.d(d), 
.reset(reset), 
.clk(clk), 
.q(q), 
.qbar(qbar)
);

initial begin
// Initialize Inputs
clk = 0;
fork
#10 d = 1;
#25 reset = 1;
#35 reset = 0;
#50 d = 0;
join
end
   always #2 clk = !clk;   
endmodule

Output Waveform of Master Slave D FF

Block Diagram of Master Slave D FF

Master Slave D Flip Flop Verilog Code

MASTER SLAVE D FLIP FLOP

In SR flip flop when the conditions SET and RESET both are 1 the that condition is known as forbidden condition. This tries to change the both Q and Q’ to be 1 and whichever will turn 1 first will further control the latch which is certainly we don’t want. This can be avoided when both S and R inputs are short circuited with a not gate in between. This prevents the forbidden condition of S and R to be 1. This combination is what we call D – Flip Flop. Thus we require only single data known as D for this FF. The output Q changes whenever D is applied with any input bit.

Whenever the clock goes from low to high i.e. posedge the input is read and fed to the output. Whenever the clock goes from high to low i.e. negedge the previous output is retained back or in easy words it remains the same.

The basic D Flip Flop is improved using a Master Slave condition. Here two D flip flops are used and the clock of Master D FF is inverted and then fed to the clock of the Slave D FF. The output Q of Master FF is fed to the input D of Slave FF. Thus when clock goes low to high the Master reads the input and stores the output. During this phase the Slave FF remains locked.

When the clock goes from High to low the Slave FF gets activated and the Master gets locked. Since during negede Master retains the output thus it acts as input for Slave and output is obtained. Master Slave condition is used because it avoids the race around condition of toggling output multiple times in a single clock cycle.

Code for Master Slave D type FF

module Mas(d,reset,clk,q,qbar);

 input d,clk,reset;

 output q,qbar;

 Master Masterr(d,reset,clk,qx,qbarx);

 Master Slave(qx,reset,!clk,q,qbar);

endmodule

module Master(d,reset,clk,q,qbar);

 input d,reset,clk;

 output reg q,qbar;

 initial

  q = 0;

 always @(posedge clk)begin

  if(~reset)begin

   q <= d;

   qbar <= !d;

  end

  else begin

   q <= 1'bx;

   qbar <= 1'bx;

 end

 end

endmodule

Testbench for Master Slave D FF

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: Shashi Suman
//
// Create Date:   19:30:41 05/12/2025
// Design Name:   Mas
// Module Name:   F:/Season 1/Master/TestMas.v
// Project Name:  Master
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Mas
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module TestMas;

// Inputs
reg d;
reg reset;
reg clk;

// Outputs
wire q;
wire qbar;

// Instantiate the Unit Under Test (UUT)
Mas uut (
.d(d), 
.reset(reset), 
.clk(clk), 
.q(q), 
.qbar(qbar)
);

initial begin
// Initialize Inputs
clk = 0;
fork
#10 d = 1;
#25 reset = 1;
#35 reset = 0;
#50 d = 0;
join
end
   always #2 clk = !clk;   
endmodule

Output Waveform of Master Slave D FF

Block Diagram of Master Slave D FF

Verilog Code for D Flip Flop

D FLIP FLOP

D flip flop stands for Delay Flip Flop. It acts as a buffer which delays the output by a clock cycle or as per desired. It’s a bistable multivibrator. D Flip Flop stores a single bit of data at a time. 
It has two inputs. The first is the D. The second is the clock. Outputs are Q returning the state of machines and another is the complement of Q. 

Truth Table

D	CLK	Q	Q’
0	↑	0	1
1	↑	1	0
X	0	Q	Q’
X	1	Q	Q’

Assuming that we have considered the clock as positive edge for the D Flip Flop. When we apply 0 at the input D at the posedge the output is triggered and input is passed which here will be 0. At the negative edge of the same clock cycle the value of Q will retain and any change in the value of D won't affect the the value of Q. The complement of Q which is 1 here also remains in same state.
 When we have 1 as input at D the output Q follows the same and gets triggered to 1. At the same moment the complement becomes 0.
The point here is setting Q to zero resets the D Flip Flop and setting Q to 1 sets the D flip flop.

Q -> 0 ( Reset when D = 0 )
Q -> 1 ( Set when D = 1 ) 
Whatever the FF captures the output gets the same captures data.

The following code is of Positive triggered FF. We can even do it for negative triggering. Al we have to do is to replace “posedge” to “negedge”

Code for D-FF (posedge)

module DFF(a,clk,b,bbar,reset);

 input a,clk,reset;

 output reg b;

 output reg bbar;

 initial begin

 b = 0;

 bbar = 1;

 end

 always @(posedge clk)begin

  if(~reset)begin

   b <= a;

   bbar <= ~a;

  end

  else begin

   b <= 1'bx;

   bbar <= 1'bx;

  end

 end

endmodule

Code for D-FF (negedge)

module DFF(a,clk,b,bbar,reset);

 input a,clk,reset;

 output reg b;

 output reg bbar;

 initial begin

 b = 0;

 bbar = 1;

 end

 always @(negedge clk)begin

  if(~reset)begin

   b <= a;

   bbar <= ~a;

  end

  else begin

   b <= 1'bx;

   bbar <= 1'bx;

  end

 end

endmodule

Code for Testbench of D-FF (Any edge)

module DFFtest;

// Inputs

reg a;

reg clk;

reg reset;

wire b;

   wire bbar;

DFF uut (

.a(a), 

.clk(clk), 

.b(b),

.reset(reset),

.bbar(bbar)

);

initial begin

// Initialize Inputs

fork 

a <= 0;

reset <= 0;

clk <= 0;

#10 a <= 1;

#15 reset <= 1;

#21 reset <= 0;

#40 a <= 0;

join

end

  always #1 clk=!clk;    

endmodule

Output Waveform

 

So Long

Verilog Code for D Flip Flop

D FLIP FLOP

D flip flop stands for Delay Flip Flop. It acts as a buffer which delays the output by a clock cycle or as per desired. It’s a bistable multivibrator.

Truth Table

D	CLK	Q	Q’
0	↑	0	1
1	↑	1	0
X	0	Q	Q’
X	1	Q	Q’

Whatever the FF captures the output gets the same captures data.

The following code is of Positive triggered FF. We can even do it for negative triggering. Al we have to do is to replace “posedge” to “negedge”

Code for D-FF (posedge)

module DFF(a,clk,b,bbar,reset);

 input a,clk,reset;

 output reg b;

 output reg bbar;

 initial begin

 b = 0;

 bbar = 1;

 end

 always @(posedge clk)begin

  if(~reset)begin

   b <= a;

   bbar <= ~a;

  end

  else begin

   b <= 1'bx;

   bbar <= 1'bx;

  end

 end

endmodule

Code for D-FF (negedge)

module DFF(a,clk,b,bbar,reset);

 input a,clk,reset;

 output reg b;

 output reg bbar;

 initial begin

 b = 0;

 bbar = 1;

 end

 always @(negedge clk)begin

  if(~reset)begin

   b <= a;

   bbar <= ~a;

  end

  else begin

   b <= 1'bx;

   bbar <= 1'bx;

  end

 end

endmodule

Code for Testbench of D-FF (Any edge)

module DFFtest;

// Inputs

reg a;

reg clk;

reg reset;

wire b;

   wire bbar;

DFF uut (

.a(a), 

.clk(clk), 

.b(b),

.reset(reset),

.bbar(bbar)

);

initial begin

// Initialize Inputs

fork 

a <= 0;

reset <= 0;

clk <= 0;

#10 a <= 1;

#15 reset <= 1;

#21 reset <= 0;

#40 a <= 0;

join

end

  always #1 clk=!clk;    

endmodule

Output Waveform

 

So Long