SR Flip Flop Verilog Code


SR Flip Flop Verilog Code

The SR or Set-Reset Flip Flop works a memory storage element. It can store a single bit memory working with two inputs named set and reset. When the output Q is 0 then the flip flop is said to be reset and when it is 1 then it is said to be Set. The output remains between 0 and 1 and is entirely dependent on the inputs.

However, one must not get confused with SR Latch and SR Flip Flop. It must be remembered that a latch is level triggered and a flip flop is edge triggered. Also the SR Latch does not have any feedback, whereas the SR Flip Flop has feedback from its output. Similarly like latch an SR Flip Flop can be contrasted with both NAND gates as well as Nor Gate as both serve as the universal gates.

The output of SR Flip Flop is called Qn+1 and Q’n+1 (Q bar). There always exists a present value of Q, so the actual output gives the next value of Q hence the name Qn+1. The outputs are always inverted, i.e. if Qn+1 is x then Q’n+1 will always be the 1s component of x. Here x is a single bit, hence either it can be 0 or 1. Because of this toggling effect we call this device as “Flip-Flop” i.e. it keeps on flipping and flopping.


NAND SR Flip Flop

NAND GATE SR Flip Flop

At the NAND gate flip flop construction is very simple with two NAND gates. One of the inputs is S’ which goes to a first input of a NAND gate. The other input R’ is in conjunction with the other NAND gate. The output of the gate associated with the R input has output Q’ which also acts as the input of the first NAND gate. Thus now the first NAND gate has two inputs, namely S’ and Q’n+1. In similar fashion the other hand gate also has two inputs, namely R’ and Qn+1. Here Qn+1 and Q’n+1 act as the feedback to NAND gates and thus they are able to store one bit. This formation of NAND gates is also called bi-stable latch.

Now let us assume that initially Qn was 0 thus it is clear that Q’n is 1.
Now, assuming

Step1: When S=0 and R=0 so S’=1 and R’=1 thus GATE1 output will be 0 and GATE2                 output will be 1.
Step2: When S=0 and R=1 then GATE1 output will be 0 and GATE2 output will be 1.
Step3: When S=1 and R=0 then GATE1 output will be 1 and GATE2 output will be 0.
Step4: When S=1 and R=1 then GATE1 output will be 1 and GATE2 output will be 0.


Now let Qn+1 be 1 and Q’n+1 = 0
Step1: When S=0 and R=0 so S’=1 and R’=1 thus GATE1 output will be 1 and GATE2                  output will be 0.
Step2: When S=0 and R=1 then GATE1 output will be 0 and GATE2 output will be 1.
Step3: When S=1 and R=0 then GATE1 output will be 1 and GATE2 output will be 0.
Step4: When S=1 and R=1 then GATE1 output will be 1 and GATE2 output will be 0.

Thus, for both Qn=0, 1 while S = 0 and R = 0 Qn+1 remain the initial value Qn. This condition is called no-change. Whenever has S = 0 and R = 1 Qn+1 is set to 0 for both conditions( Either Qn = 0 or 1 ). This is called reset condition. When we have S = 1 and R = 0 Qn+1 is set to 1 for both conditions( Either Qn = 0 or 1 ). This condition is called Set Condition.



Characteristic Table of SR Flip Flop

Qn
S
R
Qn+1
Q’n+1
Condition
0
0
0
Qn
Q’n
No Change
0
0
1
0
1
Reset
0
1
0
1
0
Set
0
1
1
X
X
Forbidden
1
0
0
Qn
Q’n
No Change
1
0
1
0
1
Reset
1
1
0
1
0
Set
1
1
1
X
X
Forbidden

Equation   Qn+1 =   S + ~R.Qn 


However the inputs S = 1 and R = 1 becomes undesirable and impact drastically on the system performance. During this while the clock is 1 the output keeps toggling between 0 and 1 or both Q and Qbar will be of same value which is the race condition her as Qbar must be the complement of Q. If any toggle precedes the other by speed, then the flip flop will certainly reach into the other state which may not be required by the user or the machine. 
This forbidden condition is removed by the JK Flip Flop (Click to View)

NOR Gate SR Flip Flop

Truth Table for Nor Gate SR Flip Flop

Qn
S
R
Qn+1
Q’n+1
Condition
0
0
0
Qn
Q’n
No Change
0
0
1
1
0
Set
0
1
0
0
1
Reset
0
1
1
X
X
Forbidden
1
0
0
Qn
Q’n
No Change
1
0
1
1
0
Set
1
1
0
0
1
Reset
1
1
1
X
X
Forbidden

NOR SR Flip Flop


Enable SR Flip Flop

In this mode the flip flop has an enable pin. The enable pin when set to 0 disables the flip flop hence the output Q and Q’ remain  0 irrespective with the inputs applied. When the enable pin turns 1 then output starts getting value with respect to input applied. Connect the enable to a timer or a clock and we get a clocked SR Flip Flop.


SR Flip Flop Verilog Code 


//////////////////////////////////////////////////////////////////
module Main(input S,
    input R,
    input clk,
    output Q,
    output Qbar
    );
    reg M,N;

always @(posedge clk) begin
M <= !(S & clk);
N <= !(R & clk);
end
assign Q = !(M & Qbar);
assign Qbar = !(N & Q);

endmodule


 TestBench
module TestSR;

 // Inputs
reg S;
reg R;
reg clk;

 // Outputs
wire Q;
wire Qbar;

 // Instantiate the Unit Under Test (UUT)
Main uut (
.S(S), 
.R(R), 
.clk(clk), 
.Q(Q), 
.Qbar(Qbar)
);

 initial begin
// Initialize Inputs
S = 0;
      R = 0;
      clk = 0;
  fork
  #2 S = 0;
  #2 R = 1;
  #4 S = 0;
  #4 R = 0;
  #6 S = 0;
  #6 R = 1;
  #8 S = 1;
  #8 R = 0;
  #10 S = 1;
  #10 R = 1;
  join
end
always #1 clk =! clk;
      
endmodule




Output waveform with Race Condition

Fig- SR Flip Flop with forbidden condition in red box

 Now according to truth table when S=0 and R=0 i.e. S'=1 and R' = 1 then we have a race condition or as we know the forbidden condition.
In the output for S = R = 0 (S' = R' = 1 ) Q is 1 and Qbar is also 1. This opposes the fact that Qbar is complement of Q. This is what we call the forbidden condition of SR Flip Flop in Red Box above

 To avoid this condition we use Master Slave SR Flip Flop 
Master Slave FF uses clock. The clock is applied to the master at posedge of clock. At this time the inverted clock is sent to slave thus for slave its negedge and hence it will halt and output will remain stable. When the master is done, clock turn to negedge hence Master halts and the inputs remain stable. The clock turns posedge for Slave which acts to its inputs which were the output of Master. This prevents the race condition of the SR Flip Flop

Verilog Code for SR Flip Flop Master Slave

module SR(
    input S,
    input R,
input clk,
    output Q,
    output Qbar
    );
and (y,S,clk);
nor (Q,Qbar,y);
and (z,R,clk);
nor (Qbar,z,Q);
 

endmodule

 TestBench

 module testSR;

 // Inputs
reg [0:0] S;
reg [0:0] R;
reg clk;
// Outputs
wire [0:0] Q;
wire [0:0] Qbar;
wire [0:0] Qx;
wire [0:0] Qbarx;
// Instantiate the Unit Under Test (UUT)
SR uut (
.S(S), 
.R(R), 
.clk(clk),
.Q(Qx), 
.Qbar(Qbarx)
);
initial begin
// Initialize Inputs
S = 0;
R = 0;
clk = 0;
fork
#8 S = 0;
#8 R = 1;
#16 S = 1;
#16 R = 0;
#24 S = 1;
#24 R = 1;
#32 S = 0;
#32 R = 0;
join

 end
SR slave(Qx,Qbarx,~clk,Q,Qbar);
 always #4 clk = ! clk; 
endmodule

The Output of Master Slave is of NOR based FF and is free from same Q and Qbar.



 When carefully observed this follows NOR FF SR. So we have covered SR FlipFlop with race condition and examples and resolving the condition.

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