Verilog Code for MOD 6 Counter

Verilog Code for MOD 5 Counter

As discussed in the previous post, I implemented the MOD4 and MOD 8 Counters. In this, I'll implement MOD 5 Counter. This counter will have 5 states starting from 000 to 100 and then again back to zero. However, according to the equation below,

                                                                                    N <= 2n 

you might find it vague. I mean 5 is not a power of 2. So how is it possible to design a counter which will count a non-power of 2? If you guessed by using external circuitry, then you are absolutely correct. Within this type of counters, we will have D Flip-Flops with clear flags. By intuition, we can say that just after 100, we will have to somehow clear the flip-flops' values, thus bringing the values back to zero. To calculate the minimum number of gates, we will have to use the same equation.  This gives the value of n as 3. Hence, we will have to have 3 D flip-flops to count 5 states in order to satisfy the requirements of MOD 5 counter. Here, we will be using AND gates to clear the flip-flops. OnFor UP counters, we use Q output from each flip-flop. If we assign each bit of 101 to variables A, B, and C then we have to choose only those variables which are HIGH i.e. 1. Here we will choose A and C as both of these variables are 1. Only these variables will act as an input to the AND gate. When the state reaches 5 i.e. 101, AND gate inputs will be 11 which will result in 1 and will be provided to each flip-flop. This will trigger the clear flag within each register, thus will reset each flip-flop to zero and counting of the states will start again.

Pretty Simple huh?
Let us apply the concept to reality.

Our MOD 5 counter will count 5 states i.e. from 0 to 4 and then will reset the flip-flops back to zero. One can make a careful observation that the AND gate that has been used must have some propagation delay. An ideal AND gate would hang the counter onto a single state forever. The proposed counter is an asynchronous counter as each flip-flop is not simultaneously triggered and the clock is depended from the previous flip-flop.

Here is the Verilog code for the implementation:

Here is the output

Carefully Observe that the counter partially goes into the 6th state but resets itself. This delay is because of the AND gate which takes time to compute the result. Here, have a look at the RTL schematic of the MOD 5 Counter.

In the Verilog code, I have introduced a delay of 1ns for the AND gate. Try to set it to 0 and give it a shot. You might think that you would get an ideal MOD 5 counter but it won't happen. The system will hang at 110.

Why does it happen?

Well, it happens because of edge issue. In the Verilog code, observe the always condition. It says @(posedge clk or posedge clear), which means from state 100 as soon the third flip-flop goes from 0 to 1 to make the state 101 at the positive edge of the clock, the AND gate with no delay will also turn on at the same instant. Thus counter stops as it cannot follow the two conditions at the same time. However, giving a delay will first activate the clock condition and then after the delay period arrives the clear edge which will reset the flip-flop again.

Problemo Solved!

Verilog Code for Asynchronous Counters

ASYNCHRONOUS COUNTER

Asynchronous means in terms of simple definition without external clock synchronization.

The output always remains free from clock signal. 

     Generally the first FF is clocked with main external clock and each of next FF have output of previous FF as their clock. This helps in reducing the number of FFs and additional gates hence requires less complexity.

    Now coming to the special "MOD" term. It basically stands for modulus.

When you have to design a Mod-Y counter then the basic steps include

1. The equation -: 2^x  = Y. 

2.  Now find value of X if you know basic Maths. You can use logarithms 

Thus after getting the value of X you basically get how many FFs are required hence you require X FFs to design Mod- Y UP or Down counter.

Here is the block diagram of Mod-16 or 4bit Asynchronous Counter

Now For Mod-16 we have value of X as 4 hence 4 FFs

Here is the code to test this

module dff(d,clk,q);

input d;

input clk;

wire d;

wire clk;

output q;

reg q;

initial

q = 1'b0;

always @(posedge clk)begin

q <= d;

end

endmodule

//************************Test Bench******************//

module FOURbit_up_B();

reg clk;

reg d;

wire [3:0]q;

initial

clk = 0;

always 

#1 clk = !clk;

dff a1(!q[0],clk,q[0]);

dff a2(!q[1],!q[0],q[1]);

dff a3(!q[2],!q[1],q[2]);

dff a4(!q[3],!q[2],q[3]);

endmodule

This was Aynchronous Up counter.

Pay attention here that clock input to each FF is ~Q (Q bar). Thus for Down counter the clock input after 1st FF will be from Q and not   ~Q (Q bar)

Here is the block diagram for 4 bit Down Asynchronous Counter

Notice the clock inputs to each FF after 1st FF.

Here is the code for Down Counter 4 bit

module dff(d,clk,q);
input d;
input clk;
wire d;
wire clk;
output q;
reg q;
initial
q = 1'b0;
always @(posedge clk)begin
q <= d;
end
endmodule

module FOURbit_up_B();
reg clk;
reg d;
wire [3:0]q;
initial
clk = 0;
always 
#1 clk = !clk;
dff a1(!q[0],clk,q[0]);
dff a2(!q[1],q[0],q[1]);
dff a3(!q[2],q[1],q[2]);
dff a4(!q[3],q[2],q[3]);
endmodule

and heres the simulation wave window from Xilinx iSim

Mail or Comment for any flaws here or if you have any doubts.

So Long

Verilog Code for Down Counters

DOWN COUNTERS

Hola Amigos

Down Counter can be defined in a simple way don't you think ?

It just counts. HaHa

Yes!! A counter just counts down from the maximum decimal value when all the required bits are 1 to zero.

Let me elaborate.

Let's take an example of 3 bit counter. So whats the maximum of 3bit counter i.e when all bits are 1 in other words "111" It's 7.

Similarly for 4 bits it "1111"that is 15.

Thus n-bits we require n Flip Flops.

Thus an Down counter will count from 15 down to 0 as I have stated and will again start from 15.

Lets code for a 4-bit Down Counter

module up(out,en,clk,reset);
    output reg[7:0] out;
    input en, clk, reset;
initial
out = 15;
always @(posedge clk)begin
if (reset) begin //if reset is true
  out <= 8'b00001111 ;
end 
else if (en==1 && out>0)  //if enable is high // because 1111 is 15
  out <= out - 1;
else
 out <= 15;
end

endmodule
//*************************TestBench 
module uptest();
reg en;
reg clk;
reg reset;
wire [7:0]out;

initial begin
reset=0;
clk=0;
en=1;
end

up call(out,en,clk,reset);
always #2 clk=!clk;
endmodule

 Here is the Output.

Notice the down counter and working again from 15  

Verilog Code for Up Counters

Hola Amigos

Up Counter can be defined in a simple way don't you think ?

It just counts. HaHa

Yes!! A counter just counts up to the maximum decimal value when all the required bits are 1. 

Crazy Definition  ? I agree. Let me elaborate.

Let's take an example of 3 bit counter. So whats the maximu of 3bit counter i.e when all bits are 1 in other words "111" It's 7.

Similarly for 4 bits it "1111"that is 15.

Thus n-bits we require n Flip Flops.

Thus an Up counter will count from 0 upto the maximum as I have stated ad will again start from 0.

Lets code for a 4-bit Up Counter

module up(out,en,clk,reset);
    output reg[7:0] out;
    input en, clk, reset;
initial
out = 0;
always @(posedge clk)begin
if (reset) begin //if reset is true
  out <= 8'b0 ;
end 
else if (en==1 && out<15)  //if enable is high // because 1111 is 15
  out <= out + 1;
else
 out <= 0;
end

endmodule
//*************************TestBench 
module uptest();
reg en;
reg clk;
reg reset;
wire [7:0]out;

initial begin
reset=0;
clk=0;
en=1;
#80 en=0;
end

up call(out,en,clk,reset);
always #2 clk=!clk;
endmodule

Here is the output

 
Notice after 80ns output is zero because I have set en pin to 0 in testbench.
Thus change your value of max and design your own counter.

Verilog Code of Ring Counter

RING COUNTER

Hola Amigos
Today I will be discussing with you about Ring Counter. 

A ring Counter is basically a simple counterthat counts upto n states working on the basics of shift registers. Upon each clock cycle the binary number shifts by 1 bit. Thus for n- bit binary number we have n-states. 

Remember Johnsson counter works similar was but has n/2 states.

Heres a bsic diagram explaining Ring Counter

Let the input be 1000

Thus  we the following output

Here is the code for ring counter.

Give it a shot!!

Code

module D(d,reset,clk,q);

input d;

input clk;

input reset;

output q;

reg q;

initial q = 1'b1;

always @(posedge clk)

begin

if(reset==0)

q <= d;

else

q <= 1'b0;

end

endmodule

module D2(d,clk,q);

input d;

input clk;

output q;

reg q;

initial

q = 1'b0;

always @(posedge clk)

q <= d;

endmodule

module Ring_B();

reg clk;

reg reset;

wire [3:0]q;

initial

begin

reset = 1;

clk = 0;

#45 reset = 0;

end

D ini(q[3],reset,clk,q[0]);  // for first FF

D2 rest1(q[0],clk,q[1]);      //***

D2 rest2(q[1],clk,q[2]);          // * These are rest FFs

D2 rest3(q[2],clk,q[3]);      //***

always

#5 clk = !clk ;

endmodule

and here is the output

I will be coming soon with Twisted Ring Counter

So Long