FINITE STATE MACHINE
Hola Amigos!!
I got a mail regarding Finite State Machine Code in verilog. Well I have prepared my own truth table set and sequence but it will sure help you all guys to design your own code of FSM.
I got a mail regarding Finite State Machine Code in verilog. Well I have prepared my own truth table set and sequence but it will sure help you all guys to design your own code of FSM.
I am using Mealey Machine Design for this example
Thus outputs are determined by both current state and current inputs.
Here is the question
Thus you can easily see the required sequence is 1101
Let me explain a bit.
Initially we will always be at state A. When we receive input as 1 the we found the 1st correct bit of 1101. But still we didn't get 1101 thus for input 1 from state A output will be 0 and will jump to state B. If we get 0 then it is different from what we want hence machine will remain at state A with output 0. Now if we recieve 1 then we have found 11 of 1101 thus jumps to state C still output is zero since 11 is not equal to 1101. Similarly if we get input 0 then we have found 110 of 1101 thus machine jumps to state D with still output 0 as 110 is not equal to 1101. If inputis zero then will remain at state C. Now if we get input 1 at state D then we get our sequence 1101. Hence output is 1. The next state is B. However if we get input 0 then machine will jump from state D to state A.
I hope it is clearly understood.
Heres the code-
module FSM(a,q,clk);
input [15:0]a; //THIS IS INPUT
output reg q; //THIS IS OUTPUT
input clk; //CLOCK
reg [1:0] state; //STATE
reg [15:0] c;
integer flag = 0;
initial begin
q = 0;
state = 2'b00; //initially at state A-00
end
always @(posedge clk)begin
if(flag==0)
c <= a;
flag = flag + 1;
end
always @(posedge clk)begin
$display("State = %d Bit = %b Q = %b",state,c[15],q);
if(state==2'b00 && c[15]==0)begin
state <=2'b00; // state A-00
q <= 0;
end
else if(state==2'b00 && c[15]==1) begin
state <=2'b01; // state B-01
q <= 0;
end
else if(state==2'b01 && c[15]==0)begin
state <=2'b00; //state A-00
q <= 0;
end
else if(state==2'b01 && c[15]==1) begin
state <=2'b10; //state C-10
q <= 0;
end
else if(state==2'b10 && c[15]==0) begin
state <= 2'b11; //state D-11
q <= 0;
end
else if(state==2'b10 && c[15]==1) begin
state=2'b10; //state C-10
q <= 0;
end
else if(state==2'b11 && c[15]==0) begin
state=2'b00; //state A-00
q <= 0;
end
else if(state==2'b11 && c[15]==1) begin
state=2'b01 ;
q <= 1;
end
c = c<<1; //to get the MSB of 16bit input which has to be checked with MSB of 1101
end
endmodule
TestBench-
module FSM_Mealey();
reg a;
reg clk;
wire q;
integer i;
reg [15:0] inp;
FSM finite(inp,q,clk);
initial begin
clk = 0;
inp <= 16'b1101_0010_1101_0000; //input sequence
end
always
#2 clk = !clk;
endmodule
Waveform Output
Output Table
The moment 1101 is obtained Q is 1
You can mail me at shashisuman17@aol.com for any queries
So Long
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