Verilog code for BCD to 7 Segment Display

BCD TO 7-SEGMENT DISPLAY

Hola Amigos

BCD stands for Binary Coded Decimal which runs only till 9. The main objective is to convert the binary input to a decimal number to be displayed on 7-Segment Block which looks like this

Here is the truth table for this 

"s" Represents State and A-G represents pins of 7-Seg Display

Here is the code

module bcd(a,b,c);

input [3:0]a;  // the number

wire [3:0]a;

output [6:0]b;

reg [6:0]b;

output [6:0]c;

reg [6:0]c;

always @(a)

begin

if(a==0)begin

b = 7'b1111110;          // in terms of 7-Seg "abcdefg" i.e Here a/b/c/d/e/f are on i.e "1" and G is off "0"

c = 7'b0000000;         // for this pattern we have output as zero

end

else if(a==1)begin

b = 7'b0110000;

c = 7'b0000001;

end

else if(a==2)begin

b = 7'b1101101;

c = 7'b0000010;

end

else if(a==3)begin

b = 7'b1111001;

c = 7'b0000011;

end

else if(a==4)begin

b = 7'b0110011;

c = 7'b0000100;

end

else if(a==5)begin

b = 7'b1011011;

c = 7'b0000101;

end

else if(a==6)begin

b = 7'b1011111;

c = 7'b0000110;

end

else if(a==7)begin

b = 7'b1110000;

c = 7'b0000111;

end

else if(a==8)begin

b = 7'b1111111;

c = 7'b0001000;

end

else if(a==9)begin

b = 7'b1111011;

c = 7'b0001001;

end

else begin

b = 7'bxxxxxxx;

c = 7'bxxxxxxx;

end

end

endmodule

//***********************Test Bench*****************//

module BCD_to_7_B ();

reg [3:0]a;

wire [6:0]b;

wire [6:0]c;

initial

begin

a = 0;

#5 a = 1;

#5 a = 2;

#5 a = 5;

#5 a = 3;

#5 a = 4;

end

bcd b1(a,b,c);

endmodule

Here is the iSim Output displaying the testbench upto a = 4;

Feel free to contact for any flaws.

So Long